PIC18LF2221T-I/SS【PDF 14/110 页】IC PIC MCU FLASH 2KX16 28SSOP

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Sheet目录3870

10页 11页 12页 13页 [14页]15页 16页 17页 18页

2007 Microchip Technology Inc.

DS41232D-page 109

PIC12F635/PIC16F636/639

11.22 Low-Current Sleep Mode

The Sleep command from the microcontroller, via an

SPI Interface command, places the AFE into an ultra

Low-current mode. All circuits including the RF Limiter,

except the minimum circuitry required to retain register

memory and SPI capability, will be powered down to

minimize the AFE current draw. Power-on Reset or any

SPI command, other than Sleep command, is required

to wake the AFE from Sleep.

11.23 Low-Current Standby Mode

The AFE is in Standby mode when no LF signal is

present on the antenna inputs but the AFE is powered

and ready to receive any incoming signals.

11.24 Low-Current Operating Mode

The AFE is in Low-current Operating mode when a LF

signal is present on an LF antenna input and internal

circuitry is switching with the received data.

11.25 Error Detection of AFE

Configuration Register Data

The AFE’s Configuration registers are volatile memory.

Therefore, the contents of the registers can be

corrupted or cleared by any electrical incidence such

as battery disconnect. To ensure the data integrity, the

AFE has an error detection mechanism using row and

column parity bits of the Configuration register memory

map. The bit 0 of each register is a row parity bit which

is calculated over the eight Configuration bits (from bit

1 to bit 8). The Column Parity Register (Configuration

calculated over the respective columns (Configuration

registers 0 to 5) of the Configuration bits. The STATUS

calculation. Parity is to be odd. The parity bit set or

cleared makes an odd number of set bits. The user

needs to calculate the row and column parity bits using

the contents of the registers and program them. During

operation, the AFE continuously calculates the row and

column parity bits of the configuration memory map. If

a parity error occurs, the AFE lowers the SCLK/ALERT

pin (interrupting the microcontroller section) indicating

the configuration memory has been corrupted or

unloaded and needs to be reprogrammed.

At an initial condition after a Power-On-Reset, the

values of the registers are all clear (default condition).

Therefore, the AFE will issue the parity bit error by

lowering the SCLK/ALERT pin. If user reprograms the

registers with correct parity bits, the SCLK/ALERT pin

will be toggled to logic high level immediately.

The parity bit errors do not change or affect the AFE’s

functional operation.

Table 11-4 shows an example of the register values

and corresponding parity bits.

TABLE 11-4:

AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE

Register Name

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Row Parity)

Configuration Register 01

Configuration Register 1

Configuration Register 2

Configuration Register 3

Configuration Register 4

Configuration Register 5

Configuration Register 6

(Column Parity Register)

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